Nanometer Technology Designs High-Quality Delay Tests
-
- Englisch ausgewählt
Fr. 138.00
inkl. gesetzl. MwSt.,
Beschreibung
Produktdetails
Einband
Gebundene Ausgabe
Erscheinungsdatum
20.12.2007
Abbildungen
XVIII, 140 illus., schwarz-weiss Illustrationen
Verlag
Springer UsSeitenzahl
281
Maße (L/B/H)
24.1/16/2.1 cm
Gewicht
623 g
Auflage
2008
Sprache
Englisch
ISBN
978-0-387-76486-3
Adopting new fabrication technologies not only provides higher integration and enhances performance, but also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz timing-related defects havv become a high proportion of the total chip defects. For nanometer technology designs, the stuck-at fault test alone cannot ensure a high quality level of chips. At-speed tests using the transition fault model has become a requirement in technologies below 180nm.
Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise (including IR-drop, ground bounce, and Ldi/dt) effects on chip performance, high test pattern volume, low fault/defect coverage, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.
Noch keine Bewertungen vorhanden
Verfassen Sie die erste Bewertung zu diesem Artikel
Helfen Sie anderen Kundinnen und Kunden durch Ihre Meinung.