Peng, K: Modulated Frequency Synthesizers Design for Wideband and High Efficiency Modulation
-
- Englisch ausgewählt
Fr. 69.90
inkl. gesetzl. MwSt.,
Beschreibung
Produktdetails
Einband
Taschenbuch
Erscheinungsdatum
01.02.2009
Verlag
VDMSeitenzahl
116
Maße (L/B/H)
22/15/0.7 cm
Gewicht
189 g
Sprache
Englisch
ISBN
978-3-639-12247-3
This book presents a wideband GFSK-modulated
fractional-N frequency synthesizer which using the
two-point delta-sigma modulation (TPDSM). Two
bottlenecks in this design have been rigorously
investigated. One is the nonlinear performance of
fractional-N frequency synthesizers. The other one
is the inherent gain and delay mismatch between the
two modulation points. Both nonlinear and mismatch
factors dominate the modulation accuracy in the
closed phase-locked loop (PLL). The proposed
formulation can successfully predict the
dependencies of the modulation accuracy on both
factors. The comparison of the averaged frequency
deviation and frequency-shift-keying (FSK) error
between theory and measurement shows excellent
agreement. The modulated frequency synthesizer
implemented in this study can achieve a 2.5 Mbps
data rate as well as a 15 s PLL stable time with
only 2.2 % FSK error under good design and operating
conditions.
fractional-N frequency synthesizer which using the
two-point delta-sigma modulation (TPDSM). Two
bottlenecks in this design have been rigorously
investigated. One is the nonlinear performance of
fractional-N frequency synthesizers. The other one
is the inherent gain and delay mismatch between the
two modulation points. Both nonlinear and mismatch
factors dominate the modulation accuracy in the
closed phase-locked loop (PLL). The proposed
formulation can successfully predict the
dependencies of the modulation accuracy on both
factors. The comparison of the averaged frequency
deviation and frequency-shift-keying (FSK) error
between theory and measurement shows excellent
agreement. The modulated frequency synthesizer
implemented in this study can achieve a 2.5 Mbps
data rate as well as a 15 s PLL stable time with
only 2.2 % FSK error under good design and operating
conditions.
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