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Produktbild: Power Distribution Networks in High Speed Integrated Circuits

Power Distribution Networks in High Speed Integrated Circuits

Fr. 202.00

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

23.10.2012

Verlag

Springer Us

Seitenzahl

280

Maße (L/B/H)

23.5/15.5/1.7 cm

Gewicht

470 g

Auflage

2004

Sprache

Englisch

ISBN

978-1-4613-5057-6

Beschreibung

Rezension

From the reviews:



"This authoritative and interesting book concentrates on explanation of behavior and design of power distribution systems for high-speed and high-complex ICs. ... It is a nice introductory text on basic principles that govern the design and operation of on-chip power distribution networks. This book is timely, and very well written. Its style is clear and readable. It should make an important reference book … . an excellent work and should be read by many of us. It is … an instructive and informative well-written book." (Mile Stojcev, Microelectronics Reliability, Vol. 44, 2004)

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

23.10.2012

Verlag

Springer Us

Seitenzahl

280

Maße (L/B/H)

23.5/15.5/1.7 cm

Gewicht

470 g

Auflage

2004

Sprache

Englisch

ISBN

978-1-4613-5057-6

Herstelleradresse

Springer-Verlag GmbH
Tiergartenstr. 17
69121 Heidelberg
DE

Email: ProductSafety@springernature.com

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  • Produktbild: Power Distribution Networks in High Speed Integrated Circuits
  • 1. Introduction.- 1.1 Evolution of integrated circuit technology.- 1.2 Evolution of design objectives.- 1.3 The problem of power distribution.- 1.4 Deleterious effects of power distribution noise.- 1.4.1 Signal delay uncertainty.- 1.4.2 On-chip clock jitter.- 1.4.3 Noise margin degradation.- 1.4.4 Degradation of gate oxide reliability.- 1.5 Book outline.- 2. Inductive Properties of Electric Circuits.- 2.1 Definitions of inductance.- 2.1.1 Field energy definition.- 2.1.2 Magnetic flux definition.- 2.1.3 Partial inductance.- 2.1.4 Net inductance.- 2.2 Variation of inductance with frequency.- 2.2.1 Uniform current density approximation.- 2.2.2 Inductance variation mechanisms.- 2.2.3 Simple circuit model.- 2.3 Inductive behavior of circuits.- 2.4 Inductive properties of on-chip interconnect.- 2.5 Summary.- 3. Properties of On-Chip Inductive Current Loops.- 3.1 Introduction.- 3.2 Dependence of inductance on line length.- 3.3 Inductive coupling between two parallel loop segments.- 3.4 Application to circuit analysis.- 3.5 Summary.- 4. Electromigration.- 4.1 Physical mechanism of electromigration.- 4.2 Electromigration-induced mechanical stress.- 4.3 Steady state limit of electromigration damage.- 4.4 Dependence of electromigration lifetime on the line dimensions.- 4.5 Statistical distribution of electromigration lifetime.- 4.6 Electromigration lifetime under AC current.- 4.7 Electromigration in novel interconnect technologies.- 4.8 Designing for electromigration reliability.- 4.9 Summary.- 5. High Performance Power Distribution Systems.- 5.1 Physical structure of a power distribution system.- 5.2 Circuit model of a power distribution system.- 5.3 Output impedance of a power distribution system.- 5.4 A power distribution system with a decoupling capacitor.- 5.4.1 Impedance characteristics.- 5.4.2 Limitations of a single-tier decoupling scheme.- 5.5 Hierarchical placement of decoupling capacitance.- 5.6 Resonance in power distribution networks.- 5.7 Full impedance compensation.- 5.8 Case study.- 5.9 Design considerations.- 5.9.1 Inductance of the decoupling capacitors.- 5.9.2 Interconnect inductance.- 5.10 Limitations of the one-dimensional circuit model.- 5.11 Summary.- 6. On-Chip Power Distribution Networks.- 6.1 Styles of on-chip power distribution networks.- 6.1.1 Basic structure of on-chip power distribution networks.- 6.1.2 Improving the impedance characteristics of on-chip power distribution networks.- 6.1.3 Evolution of power distribution networks in Alpha microprocessors.- 6.2 Allocation of on-chip decoupling capacitance.- 6.2.1 Types of on-chip decoupling capacitance.- 6.2.2 Allocation strategies.- 6.2.3 On-chip switching voltage regulator.- 6.3 Die-package interface.- 6.4 Other considerations.- 6.5 Summary.- 7. Computer-Aided Design and Analysis.- 7.1 Design flow for on-chip power distribution networks.- 7.2 Linear analysis of power distribution networks.- 7.3 Modeling power distribution networks.- 7.4 Characterizing the power current requirements of on-chip circuits.- 7.5 Numerical methods for analyzing power distribution networks.- 7.6 Summary.- 8. Inductive Properties of On-Chip Power Distribution Grids.- 8.1 Power transmission circuit.- 8.2 Simulation setup.- 8.3 Grid types.- 8.4 Inductance versus line width.- 8.5 Dependence of inductance on grid type.- 8.5.1 Non-interdigitated versus interdigitated grids.- 8.5.2 Paired versus interdigitated grids.- 8.6 Dependence of Inductance on grid dimensions.- 8.6.1 Dependence of inductance on grid width.- 8.6.2 Dependence of inductance on grid length.- 8.6.3  Sheet inductance of power grids.- 8.6.4 Efficient computation of grid inductance.- 8.7 Summary.- 9. Variation of Grid Inductance with Frequency.- 9.1 Analysis approach.- 9.2 Discussion of inductance variation.- 9.2.1 Circuit models.- 9.2.2 Analysis of inductance variation.- 9.3 Summary.- 10. Inductance/Area/Resistance Tradeoffs.- 10.1 Inductance vs. resistance tradeoff under a constant grid area constraint.- 10.2 Inductance vs. area tradeoff under a constant grid resistance constraint.- 10.3 Summary.- 11. Scaling Trends Of On-Chip Power Distribution Noise.- 11.1 Prior work.- 11.2 Interconnect characteristics.- 11.2.1 Global interconnect characteristics.- 11.2.2 Scaling of the grid inductance.- 11.2.3 Flip-chip packaging characteristics.- 11.2.4 Impact of on-chip capacitance.- 11.3 Model of power supply noise.- 11.4 Power supply noise scaling.- 11.4.1 Analysis of constant metal thickness scenario.- 11.4.2 Analysis of the scaled metal thickness scenario.- 11.4.3 ITRS scaling of power noise.- 11.5 Implications of noise scaling.- 11.6 Summary.- 12. Impedance Characteristics of Multi-Layer Grids.- 12.1 Electrical properties of multi-layer grids.- 12.1.1 Impedance characteristics of individual grid layers.- 12.1.2 Impedance characteristics of multi-layer grids.- 12.2 Case study of a two layer grid.- 12.2.1 Simulation setup.- 12.2.2 Inductive coupling between grid layers.- 12.2.3 Inductive characteristics of a two layer grid.- 12.2.4 Resistive characteristics of a two layer grid.- 12.2.5 Variation of impedance with frequency in a two layer grid.- 12.3 Design implications.- 12.4 Summary.- 13. Inductive Effects In On-Chip Power Distribution Networks.- 13.1 Scaling effects in chip-package resonance.- 13.2 Propagation of power distribution noise.- 13.3 Local inductive behavior.- 13.4 Summary.- 14. Conclusions.- References.- About the Authors.