Produktbild: Semiconductor Microchips and Fabrication

Semiconductor Microchips and Fabrication A Practical Guide to Theory and Manufacturing

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Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

30.09.2022

Verlag

John Wiley & Sons Inc

Seitenzahl

320

Maße (L/B/H)

23.5/15.7/2.2 cm

Gewicht

621 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-1-119-86778-4

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

30.09.2022

Verlag

John Wiley & Sons Inc

Seitenzahl

320

Maße (L/B/H)

23.5/15.7/2.2 cm

Gewicht

621 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-1-119-86778-4

Herstelleradresse

Libri GmbH
Europaallee 1
36244 Bad Hersfeld
DE

Email: GPSR Kontakt

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  • Produktbild: Semiconductor Microchips and Fabrication
  • Author Biography xi

    Preface xiii

    1 Introduction to the Basic Concepts 1

    1.1 What Is a Microchip? 1

    1.2 Ohm's Law and Resistivity 1

    1.3 Conductor, Insulator, and Semiconductor 5

    References 5

    2 Brief Introduction of Theories 7

    2.1 The Birth of Quantum Mechanics 7

    2.2 Energy Band (Band) 11

    References 15

    3 Early Radio Communication 17

    3.1 Telegraph Technology 17

    3.2 Electron Tube 19

    References 22

    4 Basic Knowledge of Electric Circuits (Circuits) 23

    4.1 Electric Circuits and the Components 23

    4.2 Electric Field 26

    4.3 Magnetic Field 28

    4.4 Alternating Current 30

    5 Further Discussion of Semiconductors and Diodes 33

    5.1 Semiconductor Energy Band 33

    5.2 Semiconductor Doping 36

    5.3 Semiconductor Diode 42

    References 46

    6 Transistor and Integrated Circuit 47

    6.1 Bipolar Transistor 47

    6.2 Junction Field Effect Transistor 49

    6.3 Metal-Semiconductor Field Effect Transistor 52

    6.4 Metal-Insulator-Semiconductor Field Effect Transistor 55

    References 60

    7 The Development History of Semiconductor Industry 61

    7.1 The Instruction of Semiconductor Products and Structures 61

    7.2 A Brief History of the Semiconductor Industry 63

    7.3 Changes in the Size of Transistors and SiliconWafers 65

    7.4 Clean Room 67

    7.5 Planar Process 71

    References 75

    8 Semiconductor Photonic Devices 77

    8.1 Light-Emitting Devices and Light-Emitting Principles 77

    8.2 Light-Emitting Diode (LED) 82

    8.3 Semiconductor Diode Laser 88

    8.3.1 Resonant Cavity 89

    8.3.2 Reflection and Refraction of Light 91

    8.3.3 Heterojunction Materials 93

    8.3.4 Population Inversion and Threshold Current Density 94

    References 96

    9 Semiconductor Light Detection and Photocell 97

    9.1 Digital Camera and CCD 97

    9.2 Photoconductor 100

    9.3 Transistor Laser 101

    9.4 Solar Cell 105

    References 106

    10 Manufacture of Silicon Wafer 109

    10.1 From Quartzite Ore to Polysilicon 110

    10.2 Chemical Reaction 113

    10.3 Pull Single Crystal 115

    10.4 Polishing and Slicing 116

    References 123

    11 Basic Knowledges of Process 125

    11.1 The Structure of Integrated Circuit (IC) 125

    11.2 Resolution of Optical System 128

    11.3 Why Plasma Used in the Process 131

    References 133

    12 Photolithography (Lithography) 135

    12.1 The Steps of Lithography Process 135

    12.1.1 Cleaning 135

    12.1.2 Dehydration Bake 136

    12.1.3 Photoresist Coating 138

    12.1.4 Soft Bake 141

    12.1.5 Alignment and Exposure 141

    12.1.6 Developing 145

    12.1.7 Inspection 146

    12.1.8 Hard Bake 147

    12.1.9 Descum 148

    12.2 Alignment Mark (Mark) Design on the Photomask 152

    12.3 Contemporary Photolithography Equipment Technologies 156

    References 159

    13 Dielectric Films Growth 161

    13.1 The Growth of Silicon Dioxide Film 162

    13.1.1 Thermal Oxidation Process of SiO2 162

    13.1.2 LTO Process 164

    13.1.3 PECVD Process of Silicon Dioxide 166

    13.1.4 TEOS + O3 Deposition Using APCVD System 167

    13.2 The Growth of Silicon Nitride Film 168

    13.2.1 LPCVD 168

    13.2.2 PECVD Process of Silicon Nitride 171

    13.3 Atomic Layer Deposition Technique 174

    References 177

    14 Introduction of Etching and RIE System 179

    14.1 Wet Etching 179

    14.2 RIE System for Dry Etching 182

    14.2.1 RIE Process Flow and Equipment Structure 182

    14.2.2 Process Chamber 184

    14.2.3 Vacuum Pumps 186

    14.2.4 RF Power Supply (Source) and Matching Network (Matchwork) 187

    14.2.5 Gas Cylinder and Mass Flow Controller (MFC) 189

    14.2.6 Heater and Coolant 194

    References 196

    15 Dry Etching 197

    15.1 The Etch Profile of RIE 197

    15.1.1 Case 1 198

    15.1.2 Case 2 201

    15.2 Etching Rate of RIE 203

    15.3 Dry Etching of III-V Semiconductors and Metals 206

    15.4 Etch Profile Control 207

    15.4.1 Influence of the PR Opening Shape on the Etch Profile 208

    15.4.2 The Effect of Carbon on Etching Rate and Profile 209

    15.5 Other Issues 211

    15.5.1 The Differences Between RIE and PECVD 211

    15.5.2 The Difference Between Si and SiO2 Dry Etching 214

    15.6 Inductively Coupled Plasma (ICP) Technique and Bosch Process 215

    15.6.1 Inductively Coupled Plasma Technique 216

    15.6.2 Bosch Process 219

    References 223

    16 Metal Processes 225

    16.1 Thermal Evaporation Technique 225

    16.2 Electron Beam Evaporation Technique 227

    16.3 Magnetron Sputtering Deposition Technique 231

    16.4 The Main Differences Between Electron Beam (Thermal) Evaporation and Sputtering Deposition 234

    16.5 Metal Lift-off Process 235

    16.6 Metal Selection and Annealing Technology 241

    16.6.1 The Selection of Metals 241

    16.6.2 Metal Annealing 242

    References 243

    17 Doping Processes 245

    17.1 Basic Introduction of Doping 245

    17.2 Basic Principles of Diffusion 246

    17.3 Thermal Diffusion 247

    17.4 Diffusion and Redistribution of Impurities in SiO2 248

    17.5 Minimum Thickness of SiO2 Masking Film 250

    17.6 The Distribution of Impurities Under the SiO2 Masking Film 251

    17.7 Diffusion Impurity Sources 252

    17.8 Parameters of the Diffusion Layer 255

    17.9 Four-Point Probe Sheet Resistance Measurement 256

    17.10 Ion Implantation Process 257

    17.11 Theoretical Analysis of Ion Implantation 259

    17.12 Impurity Distribution after Implantation 260

    17.13 Type and Dose of Implanted Impurities 262

    17.14 The Minimum Thickness of Masking Film 263

    17.15 Annealing Process 264

    17.16 Buried Implantation 266

    17.16.1 Implantation through Masking Film 266

    17.16.2 SOI Manufacture 267

    References 270

    18 Process Control Monitor, Packaging, and the Others 271

    18.1 Dielectric Film Quality Inspection 271

    18.2 Ohmic Contact Test 273

    18.3 Metal-to-Metal Contact 274

    18.4 Conductive Channel Control 277

    18.5 Chip Testing 278

    18.6 Dicing 279

    18.7 Packaging 280

    18.8 Equipment Operation Range 281

    18.9 Low-k and High-k Dielectrics 282

    18.9.1 Copper Interconnection and Low-k Dielectrics 283

    18.9.2 Quantum Tunneling Effect and High-k Dielectrics 286

    18.10 End 291

    References 293

    Index 295