Logic Synthesis and Verification Algorithms
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- Hardcover
- Taschenbuch ausgewählt
- eBook
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Sprache:Englisch
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Auflage:1996
Fr. 96.90
inkl. gesetzl. MwSt.,
Beschreibung
Produktdetails
Einband
Taschenbuch
Erscheinungsdatum
10.02.2006
Abbildungen
XXXII, 564 p.
Verlag
Springer UsSeitenzahl
564
Maße (B/H)
15.5/23.5 cm
Gewicht
1830 g
Auflage
1996
Sprache
Englisch
ISBN
978-0-387-31004-6
Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebras, local search, and algebraic factorization.
Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.
Circuit designers and CAD tool developers alike will find Logic Synthesis and Verification Algorithms useful as an introductory and reference text. The rich collection of examples and solved problems make this book ideal for self study.
Because of its careful balance of theory and application, Logic Synthesis and Verification Algorithms will serve well as a textbook for upper division and first year graduate students in electrical and computer engineering.
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