Cache and Interconnect Architectures in Multiprocessors
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- Hardcover ausgewählt
- Taschenbuch
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Sprache:Englisch
Fr. 145.00
inkl. gesetzl. MwSt.,
Beschreibung
Produktdetails
Einband
Gebundene Ausgabe
Erscheinungsdatum
31.07.1990
Abbildungen
XIV, 277 p.
Herausgeber
Michel Dubois + weitereVerlag
Springer UsSeitenzahl
277
Maße (L/B/H)
23.4/15.6/1.8 cm
Gewicht
592 g
Auflage
1990 edition
Sprache
Englisch
ISBN
978-0-7923-9074-9
Cache And Interconnect Architectures In Multiprocessors Eilat, Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia Shreekant S. Thakkar SequentComputerSystems The aim of the workshop was to bring together researchers working on cache coherence protocols for shared-memory multiprocessors with various interconnect architectures. Shared-memory multiprocessors have become viable systems for many applications. Bus based shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax) are currently limited to 32 processors. The fIrst goal of the workshop was to learn about the performance ofapplications on current cache-based systems. The second goal was to learn about new network architectures and protocols for future scalable systems. These protocols and interconnects would allow shared-memory architectures to scale beyond current imitations. The workshop had 20 speakers who talked about their current research. The discussions were lively and cordial enough to keep the participants away from the wonderful sand and sun for two days. The participants got to know each other well and were able to share their thoughts in an informal manner. The workshop was organized into several sessions. The summary of each session is described below. This book presents revisions of some of the papers presented at the workshop.
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