YELLAMPALLI, S: Quiescent Current Testing of CMOS Data Conve
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Beschreibung
Produktdetails
Einband
Taschenbuch
Verlag
VDMSeitenzahl
120
Maße (L/B/H)
0.7/15/22 cm
Gewicht
195 g
Sprache
Deutsch
ISBN
978-3-8364-9517-2
Power supply quiescent current (IDDQ) testing has
been very effective in detecting physical defects
such as open, short and bridging defects in VLSI
circuits designed in CMOS processes. However, in
sub-micron VLSI circuits, IDDQ current is masked by
the increased subthreshold (leakage) current of
MOSFETs affecting the efficiency of IDDQ testing. In
this work, an attempt has been made to perform robust
IDDQ testing in presence of increased leakage current
by suitably modifying some of the test methods
normally used in industry. In this book we have
re-examined both IDDQ and Delta IDDQ methods of
testing CMOS VLSI circuits and added features to
minimize the influence of leakage current. We have
designed built-in current sensors (BICS) for on-chip
testing of analog and mixed-signal integrated
circuits. We have also combined quiescent current
testing with oscillation and transient current
techniques to map large number of manufacturing
defects on a chip.
been very effective in detecting physical defects
such as open, short and bridging defects in VLSI
circuits designed in CMOS processes. However, in
sub-micron VLSI circuits, IDDQ current is masked by
the increased subthreshold (leakage) current of
MOSFETs affecting the efficiency of IDDQ testing. In
this work, an attempt has been made to perform robust
IDDQ testing in presence of increased leakage current
by suitably modifying some of the test methods
normally used in industry. In this book we have
re-examined both IDDQ and Delta IDDQ methods of
testing CMOS VLSI circuits and added features to
minimize the influence of leakage current. We have
designed built-in current sensors (BICS) for on-chip
testing of analog and mixed-signal integrated
circuits. We have also combined quiescent current
testing with oscillation and transient current
techniques to map large number of manufacturing
defects on a chip.
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