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Produktbild: Energy-Efficient Distributed Computing Systems

Energy-Efficient Distributed Computing Systems

Aus der Reihe Wiley Series on Parallel and Distributed Computing

Fr. 203.00

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

21.08.2012

Herausgeber

Albert Y. Zomaya + weitere

Verlag

John Wiley & Sons

Seitenzahl

856

Maße (L/B/H)

23.6/16.3/5.1 cm

Gewicht

1279 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-0-470-90875-4

Beschreibung

Produktdetails

Einband

Gebundene Ausgabe

Erscheinungsdatum

21.08.2012

Herausgeber

Verlag

John Wiley & Sons

Seitenzahl

856

Maße (L/B/H)

23.6/16.3/5.1 cm

Gewicht

1279 g

Auflage

1. Auflage

Sprache

Englisch

ISBN

978-0-470-90875-4

Herstelleradresse

Libri GmbH
Europaallee 1
36244 Bad Hersfeld
DE

Email: gpsr@libri.de

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  • Produktbild: Energy-Efficient Distributed Computing Systems
  • PREFACE xxix

    ACKNOWLEDGMENTS xxxi

    CONTRIBUTORS xxxiii

    1 POWER ALLOCATION AND TASK SCHEDULING ON MULTIPROCESSOR COMPUTERS WITH ENERGY AND TIME CONSTRAINTS 1
    Keqin Li

    1.1 Introduction 1

    1.1.1 Energy Consumption 1

    1.1.2 Power Reduction 2

    1.1.3 Dynamic Power Management 3

    1.1.4 Task Scheduling with Energy and Time Constraints 4

    1.1.5 Chapter Outline 5

    1.2 Preliminaries 5

    1.2.1 Power Consumption Model 5

    1.2.2 Problem Definitions 6

    1.2.3 Task Models 7

    1.2.4 Processor Models 8

    1.2.5 Scheduling Models 9

    1.2.6 Problem Decomposition 9

    1.2.7 Types of Algorithms 10

    1.3 Problem Analysis 10

    1.3.1 Schedule Length Minimization 10

    1.3.1.1 Uniprocessor computers 10

    1.3.1.2 Multiprocessor computers 11

    1.3.2 Energy Consumption Minimization 12

    1.3.2.1 Uniprocessor computers 12

    1.3.2.2 Multiprocessor computers 13

    1.3.3 Strong NP-Hardness 14

    1.3.4 Lower Bounds 14

    1.3.5 Energy-Delay Trade-off 15

    1.4 Pre-Power-Determination Algorithms 16

    1.4.1 Overview 16

    1.4.2 Performance Measures 17

    1.4.3 Equal-Time Algorithms and Analysis 18

    1.4.3.1 Schedule length minimization 18

    1.4.3.2 Energy consumption minimization 19

    1.4.4 Equal-Energy Algorithms and Analysis 19

    1.4.4.1 Schedule length minimization 19

    1.4.4.2 Energy consumption minimization 21

    1.4.5 Equal-Speed Algorithms and Analysis 22

    1.4.5.1 Schedule length minimization 22

    1.4.5.2 Energy consumption minimization 23

    1.4.6 Numerical Data 24

    1.4.7 Simulation Results 25

    1.5 Post-Power-Determination Algorithms 28

    1.5.1 Overview 28

    1.5.2 Analysis of List Scheduling Algorithms 29

    1.5.2.1 Analysis of algorithm LS 29

    1.5.2.2 Analysis of algorithm LRF 30

    1.5.3 Application to Schedule Length Minimization 30

    1.5.4 Application to Energy Consumption Minimization 31

    1.5.5 Numerical Data 32

    1.5.6 Simulation Results 32

    1.6 Summary and Further Research 33

    References 34

    2 POWER-AWARE HIGH PERFORMANCE COMPUTING 39
    Rong Ge and Kirk W. Cameron

    2.1 Introduction 39

    2.2 Background 41

    2.2.1 Current Hardware Technology and Power Consumption 41

    2.2.1.1 Processor power 41

    2.2.1.2 Memory subsystem power 42

    2.2.2 Performance 43

    2.2.3 Energy Efficiency 44

    2.3 Related Work 45

    2.3.1 Power Profiling 45

    2.3.1.1 Simulator-based power estimation 45

    2.3.1.2 Direct measurements 46

    2.3.1.3 Event-based estimation 46

    2.3.2 Performance Scalability on Power-Aware Systems 46

    2.3.3 Adaptive Power Allocation for Energy-Efficient Computing 47

    2.4 PowerPack: Fine-Grain Energy Profiling of HPC Applications 48

    2.4.1 Design and Implementation of PowerPack 48

    2.4.1.1 Overview 48

    2.4.1.2 Fine-grain systematic power measurement 50

    2.4.1.3 Automatic power profiling and code synchronization 51

    2.4.2 Power Profiles of HPC Applications and Systems 53

    2.4.2.1 Power distribution over components 53

    2.4.2.2 Power dynamics of applications 54

    2.4.2.3 Power bounds on HPC systems 55

    2.4.2.4 Power versus dynamic voltage and frequency scaling 57

    2.5 Power-Aware Speedup Model 59

    2.5.1 Power-Aware Speedup 59

    2.5.1.1 Sequential execution time for a single workload T1(w, f ) 60

    2.5.1.2 Sequential execution time for an ON-chip/OFF-chip workload 60

    2.5.1.3 Parallel execution time on N processors for an ON-/OFF-chip workload with DOP = i 61

    2.5.1.4 Power-aware speedup for DOP and ON-/OFF-chip workloads 62

    2.5.2 Model Parametrization and Validation 63

    2.5.2.1 Coarse-grain parametrization and validation 64

    2.5.2.2 Fine-grain parametrization and validation