FPGA Based Self-test Systems Design and development of reconfigurable and automated test systems to characterize high-speed interfaces
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- Englisch ausgewählt
Fr. 67.90
inkl. gesetzl. MwSt.,
Beschreibung
Produktdetails
Einband
Taschenbuch
Erscheinungsdatum
10.11.2012
Verlag
LAP LAMBERT Academic PublishingSeitenzahl
116
Maße (L/B/H)
22/15/0.8 cm
Gewicht
191 g
Sprache
Englisch
ISBN
978-3-659-27346-9
With I/O speeds increasing rapidly, there is a need to find efficient ways of designing hardware circuits to characterize and test these high speed interfaces. Traditionally, Bit Error Rate (BER) is evaluated using software simulations and stand-alone BER test products, which are either time-consuming or expensive. In this book, I demonstrate the design and implementation of a self-contained FPGA-based systems that can be used to test these interconnects. We present a user-configurable system that is capable of generating and evaluating the ITU-T recommended test patterns simultaneously over three channels with data rates of up to 3 Gb/s per channel. This includes the design of high-speed random pattern generator designs in Verilog and C-code for the integrated Power-PC processor to handle control of the user interface. The book also includes schematics of the current system and board design ideas for the readers to design their own systems.
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