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  • Produktbild: Static Crosstalk-Noise Analysis
  • Produktbild: Static Crosstalk-Noise Analysis

Static Crosstalk-Noise Analysis For Deep Sub-Micron Digital Designs

Fr. 137.00

inkl. gesetzl. MwSt., Versandkostenfrei

Beschreibung

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

31.05.2013

Verlag

Springer Us

Seitenzahl

113

Maße (L/B/H)

23.5/15.5/0.8 cm

Gewicht

213 g

Auflage

Softcover reprint of the original 1st edition 2004

Sprache

Englisch

ISBN

978-1-4757-7949-3

Beschreibung

Rezension

"Finally, a detailed analysis of the silicon interconnect coupling problem! This book not only addresses the coupling noise problem, but formulates and proposes usable CAD algorithms. Since the uncertainty in silicon design performance and reliability due to increasing coupling noise will only get worse each silicon generation, these algorithms will quickly find a gratefulhome in many CAD solutions."

(William J. Grundmann, Intel Fellow, Intel Corporation)

"All signoff analyses - timing, coupling, power, temperature, and reliability - rely on the analysis of crosstalk noise. This book is an important contribution to the field: it provides a synthesis of analytic bounding of crosstalk effects, switching window convergence, and other recent elements of crosstalk methodology. It provides a level of understanding that will be essential for researchers, developers, and users of leading EDA tools going forward."

(Andrew B. Kahng, Professor of CSE and ECE, University of California, San Diego)

Produktdetails

Einband

Taschenbuch

Erscheinungsdatum

31.05.2013

Verlag

Springer Us

Seitenzahl

113

Maße (L/B/H)

23.5/15.5/0.8 cm

Gewicht

213 g

Auflage

Softcover reprint of the original 1st edition 2004

Sprache

Englisch

ISBN

978-1-4757-7949-3

Herstelleradresse

Springer-Verlag GmbH
Tiergartenstr. 17
69121 Heidelberg
DE

Email: GPSR Kontakt

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  • Produktbild: Static Crosstalk-Noise Analysis
  • Produktbild: Static Crosstalk-Noise Analysis
  • List of Figures
    List of Tables
    Preface

    1: Introduction
    1. Motivation
    1.1 Process Trends
    1.2 CMOS Circuitry
    2. Background and Crosstalk Effects
    2.1 Static Timing Analysis
    2.2 Crosstalk Effects
    2.3 Functional Failure
    2.4 Timing Variation
    3. Search Space Pruning
    3.1 Spatial Pruning
    3.2 Electrical Pruning
    3.3 Temporal Pruning
    3.4 Functional Pruning
    3.5 Problem Complexity v.s. Accuracy
    4. Overview

    2: Miller Factor Computation for Coupling Delay
    1. Introduction
    2. Gate Driving and Coupling Model
    2.1 Nonlinearity of Driver Model
    2.2 Driver Modeling
    3. Decoupling Approximation
    3.1 Coupling Model
    3.1.1 Bounds
    3.2 Simple Iterative Approach
    3.2.1 Convergence of the Simple Iterative Approach
    3.3 Newton-Raphson Iteration for Miller Factor
    3.4 Multiple Miller Factors for Multiple Coupling Nets
    3.5 Slew Rate (Transition Time) Calculation
    4. Nonzero Initial Voltage Correction
    4.1 Glitch Waveform Approximation
    5. Experimental Results
    6. Review of Conservativism
    7. Conclusion

    3: Convergence of Switching Window Computation
    1. Introduction
    2. Background
    2.1 Simple Upper and Lower Bounds for Switching Windows
    3. Fixed Point Computation
    3.1 Formulation
    3.2 Fixed Point Iteration for Switching Windows Computation
    3.3 Multiple Convergence Points and Unstable Fixed Point
    3.4 Tightening Bounds
    4. Coupling Models
    4.1 Noise Calculation Model
    4.2 Switching Windows Overlapping Model
    4.3 Discontinuity in Discrete Models
    4.4 Error Bound between Discrete and Continuous Models
    4.5 Non-Monotone Property
    5. Convergence of Switching Windows Computation
    5.1 Proof of Convergence
    5.2 Computational Complexity
    5.3 Convergence Rate
    5.4 Least Evaluation of Coupling RC Networks
    5.5 Speed-up of Convergence
    6. Conclusion

    4: Speeding-Up Switching Window Computation
    1. Introduction
    2. Background and Definitions
    2.1 Piecewise Linear Waveform
    3. Multiple Aggressor Alignment Problem
    4. Coupling Delay Computation in Presence of Crosstalk Noise
    4.1 Algorithm
    4.2 Convergence of Our Algorithm
    4.3 Properties of Our Algorithm
    4.4 Event Pruning
    4.5 Scheduling Technique
    5. Experimental Results
    6. Review of Conservativism
    7. Conclusion

    5: Refinement of Switching Windows
    1. Introduction
    2. Formulation and Algorithm
    2.1 Arrival Time Uncertainty in Interconnect
    2.2 Switching Window Density
    2.3 Input Timing Uncertainty
    2.4 Complexity
    2.5 Implementation Consideration
    3. Resolution and Truncation Errors
    4. Experimental Results
    5. Consideration of Slew Rates
    6. Property of Time Slots and Conservativism
    7. Conclusion

    6: Functional Crosstalk Analysis
    1. Introduction
    2. Approaches and Related Work
    3. Vector Pair Searching Algorithm
    3.1 Overview
    3.2 BCOP: Boolean Constrained Optimization Problem
    3.3 Constructing Circuit via SAT
    3.4 Maximum Noise under the Zero-Delay Model
    3.5 Fixed Delay Circuit Construction via SAT
    3.5.1 Using Timed Boolean Variables
    3.5.2 Translation of Maximum Coupling Effects into an Objective Function
    3.5.3 Boolean Constrained Optimization
    3.5.4 Discrete Required Time Analysis
    3.5.5 Structural Hashing
    3.5.6 Coarse Quantum Time
    3.5.7 Boolean Constraint Relaxation 4. Experimental Results 5. Future Work 6. Conservativism Consideration 7. Conclusions 7: Conclusions
    References