System Level Design from HW/SW to Memory for Embedded Systems 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, Foz do Iguaçu, Brazil, November 3–6, 2015, Proceedings
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- Hardcover
- Taschenbuch ausgewählt
- eBook
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Sprache:Englisch
Fr. 72.90
inkl. gesetzl. MwSt.,
Beschreibung
Produktdetails
Einband
Taschenbuch
Erscheinungsdatum
11.12.2018
Abbildungen
XII, 92 illus., schwarz-weiss Illustrationen
Herausgeber
Marcelo Götz + weitereVerlag
SpringerSeitenzahl
231
Maße (L/B/H)
23.5/15.5/1.4 cm
Gewicht
379 g
Auflage
Softcover reprint of the original 1st ed. 2017
Sprache
Englisch
ISBN
978-3-030-07917-8
This book constitutes the refereed proceedings of the 5th IFIP TC 10 International Embedded Systems Symposium, IESS 2015, held in Foz do Iguaçu, Brazil, in November 2015.
The 18 full revised papers presented were carefully reviewed and selected from 25 submissions. The papers present a broad discussion on the design, analysis and verification of embedded and cyber-physical systems including design methodologies, verification, performance analysis, and real-time systems design. They are organized in the following topical sections: cyber-physical systems, system-level design; multi/many-core system design; memory system design; and embedded HW/SW design and applications.
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